Electrically erasable programmable read only memory (EEPROM) memory cells are typically fabricated using double-poly or triple-poly processes that provide two or three layers of polysilicon (poly) material, respectively. For some conventional EEPROM structures, one of the poly layers forms a so-called “floating gate” in which electrons can be stored for long periods of time, even in high temperature applications. The memory cell can be programmed by forcing electrons onto the floating gate, and can be erased by removing electrons from the floating gate.
An EEPROM memory cell can be erased by forcing electrons to migrate away from the floating gate so that it becomes charged with positive ions. This is commonly accomplished by Fowler-Nordheim tunneling using a semiconductor device having a tunnel oxide with a thickness on the order of 70-120 angstroms disposed between a silicon substrate and the floating gate. A relatively strong electric field (e.g., greater than 10 mV/cm) is applied across the gate oxide, causing electrons to tunnel from the floating gate toward the underlying source, drain, or channel region of the semiconductor device, thereby removing electrons from the floating gate. This technique is described in greater detail, for example, in U.S. Pat. Nos. 5,792,670, 5,402,371, 5,284,784 and 5,445,792, each of which is incorporated herein by reference in its entirety.
Fowler-Nordheim tunneling can also be used to program an EEPROM memory cell by forcing electrons to tunnel into the floating gate so that it becomes charged negatively. U.S. Pat. Nos. 5,792,670 and 5,402,371, each of which is incorporated by reference herein in its entirety, describe examples in which electrons are forced to tunnel into the floating gate from a channel region beneath it.
Another way to program an EEPROM memory cell is by using hot carrier injection. In hot carrier injections, during a programming operation, electrons flowing from a source to a drain of a metal oxide silicon (MOS) transistor are accelerated by a high electric field across a channel region adjacent to an oxide layer, adjacent to the floating gate. Some of the accelerated electrons become heated near the drain junction, becoming so-called “hot electrons.” Some of the hot electrons exceed the oxide barrier height and are injected into the floating gate. This technique is described in greater detail in U.S. Pat. No. 4,698,787, which is incorporated by reference herein in its entirety.
As described above, some conventional electrically erasable programmable read only memory (EEPROM) cells have a polysilicon floating gate. These memory cells typically comprise two or three layers of polysilicon. A first polysilicon layer is conventionally used as the floating gate, which forms a part of a so-called “programming capacitor.” The second polysilicon layer is conventionally used as a control gate to control the memory cell.
Conventional EEPROM memory cells typically comprise at least two transistors coupled to the programming capacitor. One transistor is adapted to “program” the programming capacitor, i.e., to force electrons into the programming capacitor floating gate. The other transistor is adapted to “sense” the electrons stored in the programming capacitor. The two transistors are conventionally coupled to the programming capacitor with deposited metal couplings.
Conventional EEPROM cells also typically comprise an erase capacitor coupled to the programming capacitor. The erase capacitor is formed from a plurality of polysilicon layers, and is operable to remove stored electrical charge from the common floating gate.
A variety of semiconductor processes can be used to fabricate conventional EEPROM memory cells, including, but not limited to, a CMOS process and a BiCMOS process. However, other processes can also be used.
Performance of EEPROM cells can be characterized by a variety of performance parameters, including, but not limited to, a programming voltage, an erasing voltage, a programming time, an erasing time, a number of write/erase cycles, and a holding time (typically specified at high temperatures (data retention), such as 150 C or 200 C). In general, lower programming voltages, faster programming times, higher numbers of write/erase cycles, and longer data retention are desirable.
EEPROM cells can be further characterized in terms of ease of fabrication, which may be associated with the number of processing steps required to form the EERPROM cell. EEPROM cells can be still further characterized in terms of required substrate area. Ease of fabrication and substrate area are often closely related to the cost of the EEPROM cell.